Modern day world is being run by innumerous gadgets and devices. As a result, no place or time is left where the gadgets are not touching our lives. The Hardware Design & EDA group is concerned with development and verification of IP & SoC cores used by these gadgets as well as tools used for this development (Electronic Design Automation).

The Hardware & EDA group consists of highly experienced teams of engineers who are not only graduates from premier institutes of India but also possess almost 90 man years of rich experience in the area of Hardware Design & EDA tools. The group has been involved in various aspects related to hardware design, verification, and EDA tools development / verification support.

Members of the team have worked with global companies like IBM, Sun Microsystems, Alcatel, STMicro, Renesas, FreeScale, AMD, Apple (Zoran), O2 Micro, TSMC, UMC, SMIC, Dongbu, FirstSilicon, LogicVision, Synopsys & NEC Corp. It has handled customers from different geographies that include America, Europe, ASIA-Pacific, and Japan.


Focus areas of this group are as follows:

	IP Design and Verification Group has worked on development and verification of various IPs for Hardware domain. Starting from the conceptualization phase and finishing with the synthesizable phase, the group has worked on the full of IP design & verification lifecycle. The group has performed the verification task of existing IPs as well, and has also detected defects in IPs that have undergone rigorous verification stages earlier.
	SoC verification The group has worked on SoC verification involving diverse technologies that include, but not limited to, Bus Protocols checks (AMBA AHB, PCIEx), bus bridges, media IPs, peripheral interconnects etc.
	Board Design and Development The group has worked on design and development of various boards based on various bus architectures.

Focus areas of this group are as follows:

LSI Design Experience ESL Design & System Simulation ‘C’ based design & behavioral modeling Front-end logic design & verification – IP and SoC SoC integration Full Chip test bench creation ASIC Synthesis & Static Timing Analysis Post layout verification Post Silicon verification Complete FPGA design flow Board Design & Firmware

SoC / IP Design & Verification Technical Skill Set HDL: Verilog, VHDL, BDL, SystemVerilog Modeling : SystemC Protocols: AMBA AHB 2.0, AXI, PCI, PCI-X, TCP/IP, Gigabit Ethernet, I2C, CSPI, USB2.0, SATA, 1394. CORES: ARM7, ARM9, SH4, DSP (StarCore, ST DSPs) Tools: Synopsys’s VCS, Design Compiler, Physical Compiler, Prime Time, Cadence’s Verilog-XL, NC-Verilog, NC-Sim, Mentor’s Modelsim, Xilinx ISE 6.1. Significant Experience IP & Subsystem Design Tapeouts for Complex Subsystems USB2.0 SATA IEEE1394 Ethernet (100/Gigabit interface) General I/Os and Controller IPs AXI, STBus Significant Experience various technologies up to 90nm with 400MHz; Design complexity upto 5m gates

[ Back to Top ]